EDN

Applying Constrained-Random Verification to Microprocessors

Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex ...
Design-Reuse

Using Vera and Constrained-Random Verification to Improve DesignWare Core Quality

As more system-on-chip (SoC) engineers rely on re-use to cut design time and reduce risk, the demand for synthesizable cores and other forms of intellectual property (IP) continues to rise ...
Electronic Design

Remove The Processor Dilemma From Constrained-Random Verification

Block-level verification has become a fairly mature technology over the past 10 years. All of the major EDA players support constrained-random stimulus generation in the simulation testbench. As part ...
Dataquest

Cocotb verification in python can turbo-charge chip development!

Cocotb is a COroutine-based COsimulation TestBench environment for verifying VHDL and SystemVerilog RTL using python. Using open source, it will allow HDL code to bind with python code using VPI or ...
EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
Electronic Design

Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli

Verifying the integration and operation of new IP in a legacy system-on-a-chip (SoC) becomes challenging. This is true particularly when the legacy SoC environment was built using a directed test ...
Design-Reuse

Applying Constrained-Random Verification to Microprocessors

Constrained-random verification (CRV) offers a highly effective way to deal with the challenges of microprocessor verification. These verification challenges are overwhelming for many reasons: complex ...