Business Wire

PRO DESIGN Launches New proFPGA XCVU37P FPGA Module for Prototyping and Verification of High Bandwidth Memory Designs

MUNICH--(BUSINESS WIRE)--PRO DESIGN, leading supplier of FPGA based prototyping systems, today launched its new proFPGA XCVU37P FPGA module for its flexible proFPGA product family. This new FPGA ...
Semiconductor Engineering

Power Modules: A Four-Dimensional Design Challenge Calls For A Holistic Design And Verification Approach

A power module is a high-power switching circuit used in applications for electric vehicles, renewable energy, photovoltaics, wind power, and much more. Switching-element IGBTs and MOSFETs are used in ...
Semiconductor Engineering

Integration Of S-Parameters For Power Module Verification Into The Engineers’ Design Environment

Developing a power module requires enhanced design and verification methods. Currently, multiple iterations are needed to get the design done. Today, design and manufacturing processes are heavily ...
EDN

On-Chip Design Verification with Xilinx FPGAs

Xilinx Virtex-II Pro devices have redefined FPGAs. The Virtex-II Pro brings with it not only a denser and faster FPGA, but an IBM PPC 405 core and up to twenty four 3.125Gb/s high speed serial ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
Design-Reuse

A Verification Environment Creation Infrastructure for Bus-Based Systems and Modules

We present the Xilinx Platform Specification Format (PSF) for system design and verification. PSF is a plug-n-play infrastructure, which promotes IP core reusability, time-to-market reduction, and IP ...
EDN

AI for Chip Design Verification

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant Challenges facing chip design verification engineers are ...
Design-Reuse

Verification Planning for Core based Designs

Verification planning is an important and integral part of verification, irrespective of the size of the system. About 70% of the design cycle time is spent on verification; with proper verification ...