Electronic Design

Using An SPI Interface To Improve FPGA Routing

Using SPI interface to free FPGA routing resources is allowing over 90% utilization, fast timing closure and supports modular design approach without consequences. When doing designs with FPGA you are ...
Semiconductor Engineering

Power Sub-Mesh Construction To Mitigate IR Drop And Minimize Routing Overhead (Intel)

A new technical paper titled “Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization” was published by researchers at Intel Corporation and National ...
EDN

BIST grouping optimization for large-scale embedded memory design

Design-for-test (DFT) engineers often struggle to develop a memory built-in self-test (BIST) grouping plan, deciding which memories belong to which BIST group, to improve test time, routing effort, ...
Design-Reuse

Novel and efficient power grid design for lesser metal layer process SOC's

Today semiconductor industry are more emphasizing on the die size reduction and less metal layers technology process options to improve gross margins but as we are decreasing more and more die size, ...
Semiconductor Engineering

Holistic Die-to-Die Interface Design Methodology For 2.5-D Multi-Chip-Module Systems

Energy/bit optimization approach for multi-chip systems with possibility of co-optimization with the routing resources defined by the signalling pitch. December 7th, 2022 - By: Fraunhofer IIS/EAS More ...
Design-Reuse

Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)

Effective management of congestion is crucial for ensuring the efficient and reliable operation of modern integrated circuits, which are becoming increasingly complex and densely packed with millions ...