EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...
Semiconductor Engineering

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...
EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Design-Reuse

Building Your UVM Verification Environment for Cache Coherent Interconnects

The ARM® AMBA® 4 Coherency Extension (ACE™) specification was officially published more than a year ago. The main driver for the ACE spec is the need to support hardware-managed cache coherency, ...