Semiconductor Engineering

Universal Verification Methodology Coverage For Bluespec RISC-V Cores

Attempting to achieve complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and complaint with the Universal ...
Semiconductor Engineering

Universal Verification Methodology Running Out Of Steam

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
techtimes

Revolutionizing Chip Testing Through Visionary Blueprints That Transform Semiconductor Verification

Prashanth Paladugu, a leading testbench architect at Micron, is transforming semiconductor design with his revolutionary approach to verification methodologies. "With the changing semiconductor ...
EDN

IC design: A short primer on the formal methods-based verification

It’s no secret that hardware is the new currency in the chip world. It’s no longer the case that the semiconductor industry is in the hands of traditional semiconductor giants; an increasing number of ...