IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...

For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

Cerritos, CA—Corelis, Inc. introduces ScanExpress Merge, a productivity enhancing software application that extends the use of boundary-scan tools to testing and programming multi-assembly systems ...