Semiconductor Engineering

Hardware-Accelerated RTL Simulator

A technical paper titled “Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism” was published by researchers at EPFL, University of Tokyo, Sharif University, and ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Electronic Design

How to Become an RTL Simulation Expert vs. Hardware Emulation Expert

In Part 1, we reviewed the process of designing a modern hardware emulation platform. Here, we’ll look at the skills and training that are necessary to become a simulation expert and an emulation ...
Nature

Power Hardware-in-the-Loop Simulation and Testing

Power Hardware-in-the-Loop (PHIL) simulation and testing is a cutting-edge methodology that integrates actual power system components with high-fidelity computational models. This approach creates a ...
Design-Reuse

Reusable Device Simulation Models for Embedded System Virtual Platforms

As embedded systems hardware is becoming more powerful, the demand for high quality, sophisticated and compelling applications is increasing. In addition to that, due to fierce competition in the ...